As the semiconductor process technology has advanced, the number of pixels in solid-state image sensor elements formed on a semiconductor substrate, such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Device) image sensors, has tended to increase. When the number of the pixels increases, the amount of data required for outputting the image signal per one frame increases correspondingly.
It is possible to increase the amount of data for outputting an image signal per one frame period, for example, by increasing the frequency of the pixel clock for outputting a signal for one pixel (pixel signal) of the image signal and outputting the data in synchronization with the pixel clock. The pixel signal for one pixel is data of a predetermined bit number, for example, from 8 bits to about a dozen bits. The pixel data of that bit number are output in synchronization with a pixel clock.
However, if the frequency of the pixel clock is increased to shorten the cycle for outputting the pixel signal, it is possible that the circuit for receiving the image signal that is in the camera that incorporates the solid-state image sensing device may not be able to handle the image signal since the image signal is transferred at a very high transfer rate.
For this reason, it is commonplace to lower the transfer rate by increasing the bit number for outputting the pixel signal for one pixel.
For example, the following configuration is common. In the case that one pixel is constituted by 8 bits, 8 terminals are provided for outputting the 8-bit pixel data, and the configuration is such that the 8-bit pixel data are output from the 8 terminals in parallel. The pixel data for one pixel are output for one cycle (or half cycle) of the pixel clock.
In addition, to lower the transfer rate by reducing the frequency of the pixel clock, 16 output terminals are provided and the terminal for outputting for one pixel is allocated into two terminals so that the transfer rate can be halved. When the transfer rate can be halved, the frequency of the transfer clock used for receiving the signal by the circuit on the side that receives the image signal can be lowered correspondingly, so the burden on the circuit is reduced correspondingly.
When merely halving the transfer rate is insufficient, it is necessary to lower the frequency of the transfer clock further by increasing the number of the output terminals further to allocate the data into a greater number of terminals.
JP-A-2007-19583, which is published by Japan Patent Office, discloses an example of the process configuration for reducing the transfer rate of the image pixel signal.
However, a problem arises when a plurality of solid-state image sensing device with different transfer rates are prepared corresponding to the transfer rate that can be received by the circuit of the camera apparatus in which the solid-state image sensing device are incorporated; that is, a correspondingly large number of different types of solid-state image sensing device are required.
Other than the transfer rate, various modes exist as the output modes for image signal, such as the case that data for one pixel are output during one cycle of the pixel clock and the case that data for one pixel are output during half a cycle. From the viewpoint that a solid-state image sensing device is required for each of the output modes also, the number of types of the required solid-state image sensing device becomes larger.
The invention has been accomplished in view of such circumstances. It is an object of the invention to make it possible to handle various types of output modes of pixel signals with one solid-state image sensing device.